1. Field of the Invention
The present invention relates generally to insulator layers within integrated circuits. More particularly, the present invention relates to methods for forming void-free and gap-filling doped silicon oxide insulator layers upon high aspect ratio narrow line-width patterned substrate layers within integrated circuits.
2. Description of the Related Art
As integrated circuit technology has advanced and integrated circuit device and conductor element dimensions have decreased, it has become increasingly important within advanced integrated circuits to form void-free and gap-filling insulator layers upon high aspect ratio narrow line-width patterned substrate layers. Most commonly, void-free and gap-filling insulator layers are desired to be formed upon high aspect ratio narrow line-width patterned conductor layers. As is known in the art of integrated circuit design and manufacture, voids typically form within an insulator layer formed upon a high aspect ratio narrow line-width patterned substrate layer at or near the apertures between the patterns within the high aspect ratio narrow line-width patterned substrate layer due to inhomogeneous filling of those apertures with insulator layers deposited through many conventional methods. The difficulty in forming void-free and gap-filling insulator layers upon high aspect ratio narrow line-width patterned substrate layers within integrated circuits typically increases as: (1) the width of the apertures between the patterns of the narrow line-width patterned substrate layers decreases, and (2) the aspect ratio of the apertures between the patterns of the narrow line-width patterned substrate layers increases.
Also important within advanced integrated circuit manufacture is the ability to form upon high aspect ratio narrow line-width patterned substrate layers void-free and gap-filling insulator layers which are easily planarized. When planarized, such void-free and gap-filling insulator layers are desirable since in addition to being merely void-free and gap-filling they also provide an insulator layer requiring minimal additional processing prior to forming upon the insulator layer additional integrated circuit layers.
Several methods have been disclosed in the art for forming and planarizing upon high aspect ratio narrow line-width patterned substrate layers within integrated circuits void-free and gap-filling insulator layers. For example, it is known in the art that void-free and gap-filling insulator layers may be formed and planarized upon high aspect ratio narrow line-width patterned substrate layers of decreased aperture width and increased aperture aspect ratio through multiple successive deposit and etch cycles of insulator layers which may be deposited through methods and materials which are otherwise conventional in the art. Unfortunately, the use of multiple successive deposit and etch cycles for forming such insulator layers typically requires substantial additional integrated circuit processing time.
As a time saving alternative for forming and planarizing void-free and gap-filling insulator layers upon high aspect ratio narrow line-width patterned substrate layers within integrated circuits, there has recently been disclosed in the art insulator layers formed at least in part through a Chemical Vapor Deposition (CVD) method employing oxygen, ozone and Tetra Ethyl Ortho Silicate (TEOS) source material mixtures at comparatively high deposition pressures and low deposition temperatures. For example, Wang et al. in U.S. Pat. No. 4,872,947 disclose a method for forming a planarized silicon oxide insulator layer upon a patterned substrate layer within an integrated circuit through planarizing through an isotropic etch method a highly conformal void-free and gap-filling silicon oxide insulator layer formed through a Chemical Vapor Deposition (CVD) method employing ozone, oxygen and Tetra Ethyl Ortho Silicate (TEOS) source materials at a reactor pressure in excess of 10 torr. Additional refinements upon the conditions under which may be formed this highly conformal void-free and gap-filling silicon oxide insulator layer are disclosed by Wang et al. In U.S. Pat. No. 5,354,715. Further, Korceynski et al., in "Improved Sub-Micron Inter-Metal Dielectric Gap-Filling Using TEOS/Ozone APCVD," Microelectronics Manufacturing Technology, January 1992, pp.22-27, disclose an analogous Chemical Vapor Deposition (CVD) method which employs ozone, oxygen and Tetra Ethyl Ortho Silicate (TEOS) source materials for forming void-free and gap-filling silicon oxide insulator layers at atmospheric pressure. The increased pressures employed by these Chemical Vapor Deposition (CVD) methods in forming void-free and gap-filling silicon oxide insulator layers provide shorter paths through which active species must travel prior to forming upon a high aspect ratio narrow line-width patterned substrate layer those silicon oxide insulator layers. Thus, the silicon oxide gap-filling insulator layers so formed are much more likely to be formed void-free.
From the foregoing it is thus desirable in the art to provide additional alternative methods and materials through which may be efficiently formed void-free and gap-filling insulator layers upon high aspect ratio narrow line-width patterned substrate layers within integrated circuits. It is towards that goal that the present invention is directed.